Due to advancements in processing technology, complex integrated circuits (ICs) can be designed at various levels of abstraction. Using a hardware description language (HDL), circuits can be designed at the gate level, the register transfer level (RTL), and higher logical levels. When designing using an HDL, the design is often structured in a modular manner. The designer describes a module in terms of the behavior of a system, the behavior describing the generation and propagation of signals through modules of combinatorial logic from one set of registers to another set of registers. HDLs provide a rich set of constructs to describe the functionality of a module. Modules may be combined and augmented to form even higher-level modules.
Prior to implementation, an HDL-based design can be simulated to determine whether or not the design will function as required. Wasted manufacturing costs due to faulty design may thereby be avoided. Numerous tools are available for simulating circuit designs including, for example, high-level modeling systems (HLMS) and HDL simulators. Simulation of an HDL-based design comprises a compilation phase and a runtime simulation phase. In the compilation phase, input HDL source code is elaborated and executable simulation code is generated. In the runtime simulation phase, the code generated in the compilation phase is executed by a simulation engine to simulate the design.
From a user perspective, HDL simulators work by compiling the HDL-based design once, and then executing the compiled design many times during the runtime phase. Therefore, the runtime performance of HDL simulators is of critical importance, and may be more important than compile time performance.
An HDL-based design is a hierarchy of module instances whose behavior is described by HDL processes. Each port of a module instance includes an actual expression (referred to herein as an “actual”) and a formal object (referred to herein as a “formal”). The actual is used as a reference to specify connections of the port with other module instances of the HDL-based design. The formal is used to describe connections with various components within the module. For ease of reference, the formal and actual of a port may be respectively referred to as port connections or connections.
HDL simulators schedule execution of HDL statements such that global variables or signals input to the HDL statements are properly updated and race conditions between concurrent HDL statements are avoided. Simulation of HDL processes is performed over a number of simulation cycles. Each simulation cycle begins with updates to values of connections. Each connection, which may be a VHDL signal or a Verilog net/variable represents values transmitted on a wire of a circuit design. For ease of reference, VHDL signals and Verilog nets may be referred to as either signals or nets, and such terms are used interchangably herein. Each update to a connection may trigger a number of processes which model how a hardware implementation of the design would respond. Processes dependent on the updated connections are scheduled and executed in a delta cycle.